Changeset 0b05082 in mainline


Ignore:
Timestamp:
2018-07-18T18:56:16Z (6 years ago)
Author:
Jiří Zárevúcky <jiri.zarevucky@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
40abf56
Parents:
9b1baac
git-author:
Jiří Zárevúcky <jiri.zarevucky@…> (2018-07-18 14:25:11)
git-committer:
Jiří Zárevúcky <jiri.zarevucky@…> (2018-07-18 18:56:16)
Message:

Adds

  • tcb_raw_get(), which returns the value of the TP register without any offsets applied to it,
  • tcb_raw_set(), which does the opposite,
  • tcb_is_set(), which returns true iff the register is not NULL,
  • tcb_reset(), which sets the register to NULL.

Used for debug assertions.

Location:
uspace/lib/c
Files:
14 edited

Legend:

Unmodified
Added
Removed

  • uspace/lib/c/arch/abs32le/include/libarch/tls.h

    r9b1baac r0b05082  
    4141#include <stddef.h>
    4242
     43/* Some architectures store the value with an offset. Some do not. */
     44#define ARCH_TP_OFFSET 0
     45
    4346typedef struct {
    4447        void *self;
    … …  
    4649} tcb_t;
    4750
    48 static inline void __tcb_set(tcb_t *tcb)
     51static inline void __tcb_raw_set(void *tls)
    4952{
     53        /* Usually a short assembly assigning to an ABI-defined register. */
    5054}
    5155
    52 static inline tcb_t *__tcb_get(void)
     56static inline void *__tcb_raw_get(void)
    5357{
     58        /* Usually a short assembly reading from an ABI-defined register. */
    5459        return NULL;
    5560}

  • uspace/lib/c/arch/amd64/include/libarch/tls.h

    r9b1baac r0b05082  
    3838#define CONFIG_TLS_VARIANT_2
    3939
     40#define ARCH_TP_OFFSET 0
     41
    4042#include <libc.h>
    4143
    … …  
    4547} tcb_t;
    4648
    47 static inline void __tcb_set(tcb_t *tcb)
     49static inline void __tcb_raw_set(void *tls)
    4850{
    49         asm volatile ("movq %0, %%fs:0" :: "r" (tcb));
     51        asm volatile ("movq %0, %%fs:0" :: "r" (tls));
    5052}
    5153
    52 static inline tcb_t *__tcb_get(void)
     54static inline void *__tcb_raw_get(void)
    5355{
    54         tcb_t *retval;
    55 
     56        void *retval;
    5657        asm volatile ("movq %%fs:0, %0" : "=r" (retval));
    5758        return retval;

  • uspace/lib/c/arch/arm32/include/libarch/fibril.h

    r9b1baac r0b05082  
    6262                (c)->pc = (sysarg_t) (_pc); \
    6363                (c)->sp = ((sysarg_t) (stack)) + (size) - SP_DELTA; \
    64                 (c)->tls = ((sysarg_t)(ptls)) + sizeof(tcb_t) + ARM_TP_OFFSET; \
     64                (c)->tls = ((sysarg_t)(ptls)) + ARCH_TP_OFFSET; \
    6565                (c)->fp = 0; \
    6666        } while (0)

  • uspace/lib/c/arch/arm32/include/libarch/tls.h

    r9b1baac r0b05082  
    4242
    4343/** Offsets for accessing thread-local variables are shifted 8 bytes higher. */
    44 #define ARM_TP_OFFSET  (-8)
     44#define ARCH_TP_OFFSET  (sizeof(tcb_t) - 8)
    4545
    4646/** TCB (Thread Control Block) struct.
    … …  
    5353} tcb_t;
    5454
    55 
    56 /** Sets TLS address to the r9 register.
    57  *
    58  *  @param tcb          TCB (TLS starts behind)
    59  */
    60 static inline void __tcb_set(tcb_t *tcb)
     55static inline void *__tcb_raw_get(void)
    6156{
    62         uint8_t *tls = (uint8_t *) tcb;
    63         tls += sizeof(tcb_t) + ARM_TP_OFFSET;
    64         asm volatile (
    65             "mov r9, %0"
    66             :
    67             : "r" (tls)
    68         );
     57        uint8_t *ret;
     58        asm volatile ("mov %0, r9" : "=r" (ret));
     59        return ret;
    6960}
    7061
    71 
    72 /** Returns TCB address.
    73  *
    74  * @return              TCB address (starts before TLS which address is stored
    75  *                      in r9 register).
    76  */
    77 static inline tcb_t *__tcb_get(void)
     62static inline void __tcb_raw_set(void *tls)
    7863{
    79         uint8_t *ret;
    80         asm volatile (
    81             "mov %0, r9"
    82             : "=r" (ret)
    83         );
    84         return (tcb_t *) (ret - ARM_TP_OFFSET - sizeof(tcb_t));
     64        asm volatile ("mov r9, %0" :: "r" (tls));
    8565}
    86 
    8766
    8867/** Returns TLS address stored.

  • uspace/lib/c/arch/ia32/include/libarch/tls.h

    r9b1baac r0b05082  
    3838#define CONFIG_TLS_VARIANT_2
    3939
     40#define ARCH_TP_OFFSET 0
     41
    4042#include <libc.h>
    4143
    … …  
    4648} tcb_t;
    4749
    48 static inline void __tcb_set(tcb_t *tcb)
     50static inline void __tcb_raw_set(void *tls)
    4951{
    50         asm volatile ("movl %0, %%gs:0" :: "r" (tcb));
     52        asm volatile ("movl %0, %%gs:0" :: "r" (tls));
    5153}
    5254
    53 static inline tcb_t *__tcb_get(void)
     55static inline void *__tcb_raw_get(void)
    5456{
    55         tcb_t *retval;
    56 
     57        void *retval;
    5758        asm volatile ("movl %%gs:0, %0" : "=r" (retval));
    58 
    5959        return retval;
    6060}

  • uspace/lib/c/arch/ia64/include/libarch/tls.h

    r9b1baac r0b05082  
    3838#define CONFIG_TLS_VARIANT_1
    3939
     40#define ARCH_TP_OFFSET 0
     41
    4042/* This structure must be exactly 16 bytes long */
    4143typedef struct {
    … …  
    4446} tcb_t;
    4547
    46 static inline void __tcb_set(tcb_t *tcb)
     48static inline void __tcb_raw_set(void *tcb)
    4749{
    4850        asm volatile ("mov r13 = %0\n" : : "r" (tcb) : "r13");
    4951}
    5052
    51 static inline tcb_t *__tcb_get(void)
     53static inline void *__tcb_raw_get(void)
    5254{
    53         tcb_t *retval;
    54 
     55        void *retval;
    5556        asm volatile ("mov %0 = r13\n" : "=r" (retval));
    56 
    5757        return retval;
    5858}

  • uspace/lib/c/arch/mips32/include/libarch/tls.h

    r9b1baac r0b05082  
    6161 * - No assumption about DTV etc., but it will not have a fixed address
    6262 */
    63 #define MIPS_TP_OFFSET 0x7000
     63#define ARCH_TP_OFFSET (0x7000 + sizeof(tcb_t))
    6464
    6565typedef struct {
    … …  
    6767} tcb_t;
    6868
    69 static inline void __tcb_set(tcb_t *tcb)
     69static inline void __tcb_raw_set(void *tls)
    7070{
    71         uint8_t *tp = (uint8_t *) tcb;
    72         tp += MIPS_TP_OFFSET + sizeof(tcb_t);
    73 
    74         asm volatile ("add $27, %0, $0" : : "r" (tp)); /* Move tls to K1 */
     71        /* Move tls to K1 */
     72        asm volatile ("add $27, %0, $0" :: "r" (tls));
    7573}
    7674
    77 static inline tcb_t *__tcb_get(void)
     75static inline void *__tcb_raw_get(void)
    7876{
    79         uint8_t *retval;
    80 
     77        void *retval;
    8178        asm volatile ("add %0, $27, $0" : "=r" (retval));
    82 
    83         return (tcb_t *)(retval - MIPS_TP_OFFSET - sizeof(tcb_t));
     79        return retval;
    8480}
    8581

  • uspace/lib/c/arch/ppc32/include/libarch/tls.h

    r9b1baac r0b05082  
    4040#include <libc.h>
    4141
    42 #define PPC_TP_OFFSET 0x7000
     42#define ARCH_TP_OFFSET (0x7000 + sizeof(tcb_t))
    4343
    4444typedef struct {
    … …  
    4646} tcb_t;
    4747
    48 static inline void __tcb_set(tcb_t *tcb)
     48static inline void __tcb_raw_set(void *tls)
    4949{
    50         uint8_t *tp = (uint8_t *) tcb;
    51         tp += PPC_TP_OFFSET + sizeof(tcb_t);
    52 
    53         asm volatile (
    54             "mr %%r2, %0\n"
    55             :
    56             : "r" (tp)
    57         );
     50        asm volatile ("mr %%r2, %0\n" :: "r" (tls));
    5851}
    5952
    60 static inline tcb_t *__tcb_get(void)
     53static inline void *__tcb_raw_get(void)
    6154{
    62         uint8_t *retval;
    63 
    64         asm volatile (
    65             "mr %0, %%r2\n"
    66             : "=r" (retval)
    67         );
    68 
    69         return (tcb_t *) (retval - PPC_TP_OFFSET - sizeof(tcb_t));
     55        void *retval;
     56        asm volatile ("mr %0, %%r2\n" : "=r" (retval));
     57        return retval;
    7058}
    7159

  • uspace/lib/c/arch/riscv64/include/libarch/tls.h

    r9b1baac r0b05082  
    4040#include <libc.h>
    4141
     42/* Some architectures store the value with an offset. Some do not. */
     43#define ARCH_TP_OFFSET 0
     44
    4245typedef struct {
    4346        void *self;
    … …  
    4548} tcb_t;
    4649
    47 static inline void __tcb_set(tcb_t *tcb)
     50static inline void __tcb_raw_set(void *tls)
    4851{
     52        // TODO
    4953}
    5054
    51 static inline tcb_t *__tcb_get(void)
     55static inline void *__tcb_raw_get(void)
    5256{
    53         return (tcb_t *) 0;
     57        // TODO
     58        return 0;
    5459}
    5560

  • uspace/lib/c/arch/sparc64/include/libarch/tls.h

    r9b1baac r0b05082  
    4141#define CONFIG_TLS_VARIANT_2
    4242
     43#define ARCH_TP_OFFSET 0
     44
    4345typedef struct {
    4446        void *self;
    … …  
    4648} tcb_t;
    4749
    48 static inline void __tcb_set(tcb_t *tcb)
     50static inline void __tcb_raw_set(void *tcb)
    4951{
    5052        asm volatile ("mov %0, %%g7\n" : : "r" (tcb) : "g7");
    5153}
    5254
    53 static inline tcb_t *__tcb_get(void)
     55static inline void *__tcb_raw_get(void)
    5456{
    55         tcb_t *retval;
    56 
     57        void *retval;
    5758        asm volatile ("mov %%g7, %0\n" : "=r" (retval));
    58 
    5959        return retval;
    6060}

  • uspace/lib/c/generic/context.c

    r9b1baac r0b05082  
    2929#include <context.h>
    3030#include <setjmp.h>
    31 #include <libarch/tls.h>
     31#include <tls.h>
    3232#include <libarch/fibril.h>
    3333#include <libarch/faddr.h>

  • uspace/lib/c/generic/private/fibril.h

    r9b1baac r0b05082  
    3232#include <adt/list.h>
    3333#include <context.h>
    34 #include <libarch/tls.h>
     34#include <tls.h>
    3535#include <abi/proc/uarg.h>
    3636#include <atomic.h>

  • uspace/lib/c/include/fibril_synch.h

    r9b1baac r0b05082  
    3838#include <fibril.h>
    3939#include <adt/list.h>
    40 #include <libarch/tls.h>
     40#include <tls.h>
    4141#include <sys/time.h>
    4242#include <stdbool.h>

  • uspace/lib/c/include/tls.h

    r9b1baac r0b05082  
    3737
    3838#include <libarch/tls.h>
     39#include <stdbool.h>
    3940#include <stddef.h>
    4041#include <stdint.h>
     42
     43static inline void __tcb_reset(void)
     44{
     45        __tcb_raw_set(NULL);
     46}
     47
     48static inline void __tcb_set(tcb_t *tcb)
     49{
     50        __tcb_raw_set((uint8_t *)tcb + ARCH_TP_OFFSET);
     51}
     52
     53
     54static inline tcb_t *__tcb_get(void)
     55{
     56        return (tcb_t *)((uint8_t *)__tcb_raw_get() - ARCH_TP_OFFSET);
     57}
     58
     59/*
     60 * The TP register is supposed to be zero when the thread is first created
     61 * by the kernel. We use this for some debugging assertions.
     62 */
     63static inline bool __tcb_is_set(void)
     64{
     65        return __tcb_raw_get() != NULL;
     66}
    4167
    4268/** DTV Generation number - equals vector length */
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