Changeset 1a1b05b in mainline


Ignore:
Timestamp:
2012-09-18T13:58:05Z (12 years ago)
Author:
Jan Vesely <jano.vesely@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
9e96666
Parents:
4bd3f45
Message:

arm32: Enable instruction cache on armv6/v7

File:
1 edited

Legend:

Unmodified
Added
Removed

  • kernel/arch/arm32/src/cpu/cpu.c

    r4bd3f45 r1a1b05b  
    116116        control_reg &= ~CP15_R1_ALIGN_CHECK_EN;
    117117        /* Enable caching */
    118         control_reg |= CP15_R1_CACHE_EN;
     118        control_reg |= CP15_R1_CACHE_EN | CP15_R1_INST_CACHE_EN;
    119119       
    120120        asm volatile (
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