Changeset 3412e844 in mainline

Timestamp:

2012-11-24T02:28:47Z (11 years ago)

Author:

Jan Vesely <jano.vesely@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

f1e496a

Parents:

6e634d6

Message:

arm32: Implement basic support for FPU context switching.

Lazy fpu context switching is not supported, yet.

Location:

kernel/arch/arm32

Files:

• Makefile.inc (modified) (1 diff)
• include/fpu_context.h (modified) (1 diff)
• src/cpu/cpu.c (modified) (2 diffs)
• src/dummy.S (modified) (2 diffs)

kernel/arch/arm32/Makefile.inc

@@ -34 +34 @@
 
 GCC_CFLAGS += -fno-omit-frame-pointer -mapcs-frame -march=$(subst _,-,$(PROCESSOR)) -mno-unaligned-access
+
+ifeq ($(CONFIG_FPU),y)
+# This is necessary to allow vmsr insn and fpexc manipulation
+GCC_CFLAGS += -mfloat-abi=hard 
+endif
 
 BITS = 32

kernel/arch/arm32/include/fpu_context.h

@@ -41 +41 @@
 #include <typedefs.h>
 
-#define FPU_CONTEXT_ALIGN    0
+#define FPU_CONTEXT_ALIGN    8
 
+/* ARM Architecture reference manual, p B-1529.
+ * We don't enable EX bit so max 32 64bit regs are stored (+2 control regs)
+ */
 typedef struct {
+        uint32_t fpuscr;
+        uint32_t fpuexc;
+        uint32_t s[64];
 } fpu_context_t;
 

kernel/arch/arm32/src/cpu/cpu.c

@@ -38 +38 @@
 #include <arch.h>
 #include <print.h>
+#include <fpu_context.h>
 
 /** Number of indexes left out in the #imp_data array */
@@ -138 +139 @@
 }
 
+void fpu_init(void)
+{
+        //TODO: Identify FPU unit
+        //and set correct functions to save/restore ctx
+}
+
+void fpu_enable(void)
+{
+        /* Enable FPU instructions */
+        asm volatile (
+                "ldr r1, =0x40000000\n"
+                "vmsr fpexc, r1\n"
+                ::: "r1"
+        );
+}
+
+void fpu_disable(void)
+{
+        /* Disable FPU instructions */
+        asm volatile (
+                "ldr r1, =0x00000000\n"
+                "vmsr fpexc, r1\n"
+                ::: "r1"
+        );
+}
+
+void fpu_context_save(fpu_context_t *ctx)
+{
+        // TODO check and complete. What about fpexc?
+        asm volatile (
+                "vmrs r1, fpscr\n"
+//              "vmrs r2, fpexc\n"
+                "stm %0, {r1, r2}\n"
+                "vstm %0, {d0, d1, d2, d3, d4, d5, d6, d7, d8, d9, d10, d11, d12, d13, d14, d15}\n"
+                ::"r" (ctx): "r1","r2","memory"
+        );
+}
+
+void fpu_context_restore(fpu_context_t *ctx)
+{
+        // TODO check and complete. What about fpexc?
+        asm volatile (
+                "ldm %0, {r1, r2}\n"
+                "vmsr fpscr, r1\n"
+//              "vmsr fpexc, r2\n"
+                "vldm %0, {d0, d1, d2, d3, d4, d5, d6, d7, d8, d9, d10, d11, d12, d13, d14, d15}\n"
+                ::"r" (ctx): "r1","r2"
+        );
+}
+
 /** Retrieves processor identification and stores it to #CPU.arch */
 void cpu_identify(void)

kernel/arch/arm32/src/dummy.S

@@ -32 +32 @@
 .global asm_delay_loop
 
-.global fpu_context_restore
-.global fpu_context_save
-.global fpu_enable
-.global fpu_init
-
 .global sys_tls_set
 .global dummy
@@ -46 +41 @@
         mov     pc, lr
 
-fpu_context_restore:
-        mov     pc, lr
-    
-fpu_context_save:
-        mov     pc, lr
-    
-fpu_enable:
-        mov     pc, lr
-
-fpu_init:
-        mov     pc, lr
-    
 # not used on ARM
 sys_tls_set: