Changeset 561c301 in mainline

Timestamp:

2013-09-11T23:08:47Z (11 years ago)

Author:

Martin Decky <martin@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

7d771d5

Parents:

e88f3e9

Message:

remove ISA-specific stuff from the comments of generic functions
do not check whether the return value of async_exchange_begin() is NULL (the functions working with the exchange can handle it gracefully)
coding style

Location:

uspace

Files:

• drv/bus/isa/i8237.c (modified) (1 diff)
• lib/c/generic/device/hw_res.c (modified) (4 diffs)

uspace/drv/bus/isa/i8237.c

@@ -279 +279 @@
  *
  * @return Error code.
+ *
  */
 static inline int dma_controller_init(dma_controller_t *controller)

uspace/lib/c/generic/device/hw_res.c

@@ -44 +44 @@
         
         async_exch_t *exch = async_exchange_begin(sess);
-        if (exch == NULL)
-                return ENOMEM;
+        
         int rc = async_req_1_1(exch, DEV_IFACE_ID(HW_RES_DEV_IFACE),
             HW_RES_GET_RESOURCE_LIST, &count);
@@ -79 +78 @@
 {
         async_exch_t *exch = async_exchange_begin(sess);
-        if (exch == NULL)
-                return false;
+        
         int rc = async_req_1_0(exch, DEV_IFACE_ID(HW_RES_DEV_IFACE),
             HW_RES_ENABLE_INTERRUPT);
@@ -88 +86 @@
 }
 
-/**
- * Setup DMA channel to specified place and mode.
- * @param channel DMA Channel 1,2,3 for 8 bit transfers, 5,6,7 for 16 bit.
- * @param pa Physical address of the buffer. Must be < 16MB for 16 bit and < 1MB
- *           for 8 bit transfers.
- * @param size DMA buffer size, limited to 64K.
- * @param mode Mode of the DMA channel:
- *              - Read or Write
- *              - Allow automatic reset
- *              - Use address decrement instead of increment
- *              - Use SINGLE/BLOCK/ON DEMAND transfer mode
+/** Setup DMA channel to specified place and mode.
+ *
+ * @param channel DMA channel.
+ * @param pa      Physical address of the buffer.
+ * @param size    DMA buffer size.
+ * @param mode    Mode of the DMA channel:
+ *                 - Read or Write
+ *                 - Allow automatic reset
+ *                 - Use address decrement instead of increment
+ *                 - Use SINGLE/BLOCK/ON DEMAND transfer mode
+ *
  * @return Error code.
+ *
  */
 int hw_res_dma_channel_setup(async_sess_t *sess,
@@ -105 +104 @@
 {
         async_exch_t *exch = async_exchange_begin(sess);
-        if (exch == NULL)
-                return ENOMEM;
+        
         const uint32_t packed = (channel & 0xffff) | (mode << 16);
         const int ret = async_req_4_0(exch, DEV_IFACE_ID(HW_RES_DEV_IFACE),
             HW_RES_DMA_CHANNEL_SETUP, packed, pa, size);
+        
         async_exchange_end(exch);
-
+        
         return ret;
 }
 
-/**
- * Query remaining bytes in the buffer.
- * @param channel DMA Channel 1,2,3 for 8 bit transfers, 5,6,7 for 16 bit.
- * @return Number of bytes remaining in the buffer(>=0) or error code(<0).
+/** Query remaining bytes in the buffer.
+ *
+ * @param channel DMA channel.
+ *
+ * @return Number of bytes remaining in the buffer if positive.
+ * @return Error code if negative.
+ *
  */
 int hw_res_dma_channel_remain(async_sess_t *sess, unsigned channel)
 {
         async_exch_t *exch = async_exchange_begin(sess);
-        if (exch == NULL)
-                return ENOMEM;
+        
         sysarg_t remain;
         const int ret = async_req_2_1(exch, DEV_IFACE_ID(HW_RES_DEV_IFACE),
             HW_RES_DMA_CHANNEL_REMAIN, channel, &remain);
+        
         async_exchange_end(exch);
+        
         if (ret == EOK)
                 return remain;
+        
         return ret;
 }