Changeset d51cca8 in mainline


Ignore:
Timestamp:
2018-09-06T17:20:15Z (6 years ago)
Author:
Jiří Zárevúcky <jiri.zarevucky@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
7328ff4
Parents:
f8048d1
git-author:
Jiří Zárevúcky <jiri.zarevucky@…> (2018-08-11 22:57:32)
git-committer:
Jiří Zárevúcky <jiri.zarevucky@…> (2018-09-06 17:20:15)
Message:

Use <stdatomic.h> to implement uspace barriers.

Location:
uspace/lib/c
Files:
10 deleted
2 edited

Legend:

Unmodified
Added
Removed

  • uspace/lib/c/arch/sparc64/include/libarch/ddi.h

    rf8048d1 rd51cca8  
    3434#define LIBC_sparc64_DDI_H_
    3535
     36#include <barrier.h>
    3637#include <ddi.h>
    37 
    38 static inline void memory_barrier(void)
    39 {
    40         asm volatile (
    41             "membar #LoadLoad | #StoreStore\n"
    42             ::: "memory"
    43         );
    44 }
    4538
    4639static inline void arch_pio_write_8(ioport8_t *port, uint8_t v)

  • uspace/lib/c/include/barrier.h

    rf8048d1 rd51cca8  
    3636#define LIBC_COMPILER_BARRIER_H_
    3737
    38 #include <libarch/barrier.h>
     38#include <stdatomic.h>
    3939
    4040extern void smp_memory_barrier(void);
    4141
    42 #define compiler_barrier() asm volatile ("" ::: "memory")
     42static inline void compiler_barrier(void)
     43{
     44        atomic_signal_fence(memory_order_seq_cst);
     45}
     46
     47static inline void memory_barrier(void)
     48{
     49        atomic_thread_fence(memory_order_seq_cst);
     50}
     51
     52static inline void read_barrier(void)
     53{
     54        atomic_thread_fence(memory_order_acquire);
     55}
     56
     57static inline void write_barrier(void)
     58{
     59        atomic_thread_fence(memory_order_release);
     60}
    4361
    4462/** Forces the compiler to access (ie load/store) the variable only once. */
Note: See TracChangeset for help on using the changeset viewer.