Changeset e13ba75 in mainline

Timestamp:

2013-08-06T22:46:12Z (11 years ago)

Author:

Jan Vesely <jano.vesely@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

46db5c51

Parents:

f9f758e

Message:

arm32: turn more macros into inlin functions, add coherence protection

Location:

kernel/arch/arm32/include/arch/mm

Files:

• page.h (modified) (1 diff)
• page_armv4.h (modified) (1 diff)
• page_armv6.h (modified) (6 diffs)

kernel/arch/arm32/include/arch/mm/page.h

@@ -95 +95 @@
 /* Set PTE address accessors for each level. */
 #define SET_PTL0_ADDRESS_ARCH(ptl0) \
-        (set_ptl0_addr((pte_t *) (ptl0)))
+        set_ptl0_addr((pte_t *) (ptl0))
 #define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) \
-        (((pte_t *) (ptl0))[(i)].l0.coarse_table_addr = (a) >> 10)
+        set_ptl1_addr((pte_t*) (ptl0), i, a)
 #define SET_PTL2_ADDRESS_ARCH(ptl1, i, a)
 #define SET_PTL3_ADDRESS_ARCH(ptl2, i, a)
 #define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) \
-        (((pte_t *) (ptl3))[(i)].l1.frame_base_addr = (a) >> 12)
+        set_ptl3_addr((pte_t*) (ptl3), i, a)
 
 /* Get PTE flags accessors for each level. */

kernel/arch/arm32/include/arch/mm/page_armv4.h

@@ -131 +131 @@
 {
         TTBR0_write((uint32_t)pt);
+}
+
+NO_TRACE static inline void set_ptl1_addr(pte_t *pt, size_t i, uintptr_t address)
+{
+        pt[i].l0.coarse_table_addr = address >> 10;
+}
+
+NO_TRACE static inline void set_ptl3_addr(pte_t *pt, size_t i, uintptr_t address)
+{
+        pt[i].l1.frame_base_addr = address >> 12;
 }
 

kernel/arch/arm32/include/arch/mm/page_armv6.h

@@ -127 +127 @@
 #define PTE_DESCRIPTOR_SMALL_PAGE_NX    3
 
+
+//TODO: DCCMVAU should be enough but it does not work.
+#define pt_coherence_m(pt, count) \
+do { \
+        for (unsigned i = 0; i < count; ++i) \
+                DCCMVAC_write((uintptr_t)(pt + i)); \
+        read_barrier(); \
+} while (0)
+#define pt_coherence(page) pt_coherence_m(page, 1)
+
 /** Sets the address of level 0 page table.
  *
@@ -135 +145 @@
 {
         TTBR0_write((uint32_t)pt);
+}
+
+NO_TRACE static inline void set_ptl1_addr(pte_t *pt, size_t i, uintptr_t address)
+{
+        pt[i].l0.coarse_table_addr = address >> 10;
+        pt_coherence(&pt[i]);
+}
+
+NO_TRACE static inline void set_ptl3_addr(pte_t *pt, size_t i, uintptr_t address)
+{
+        pt[i].l1.frame_base_addr = address >> 12;
+        pt_coherence(&pt[i]);
 }
 
@@ -205 +227 @@
                 p->ns = 0;
         }
-        DCCMVAC_write((uint32_t)p);
-        //TODO: DCCMVAU should be enough but it does not work.
+        pt_coherence(p);
 }
 
@@ -269 +290 @@
                         p->access_permission_1 = PTE_AP1_RO;
         }
-        DCCMVAC_write((uint32_t)p);
-        //TODO: DCCMVAU should be enough but it does not work.
+        pt_coherence(p);
 }
 
@@ -281 +301 @@
         write_barrier();
         p->descriptor_type = PTE_DESCRIPTOR_COARSE_TABLE;
-        DCCMVAC_write((uint32_t)p);
-        //TODO: DCCMVAU should be enough but it does not work.
+        pt_coherence(p);
 }
 
@@ -290 +309 @@
 
         p->descriptor_type = PTE_DESCRIPTOR_SMALL_PAGE;
-        DCCMVAC_write((uint32_t)p);
-        //TODO: DCCMVAU should be enough but it does not work.
+        pt_coherence(p);
 }