Changeset 1a5eca4 in mainline for kernel/arch/amd64/src/asm.S

Timestamp:

2016-04-27T19:36:56Z (8 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

af9dd1e

Parents:

d6f9fff

Message:

amd64: Make TLS settable from uspace

The TLS document[1] mandates that %fs[0] is the thread pointer on amd64.
That is good as it allows userspace-only TLS management for fibrils:
fibril_save/restore() simply manipulate the thread pointer in %fs:0 and
don't need to ask the kernel to modify %fs's base. The kernel treats
%fs:0 as another preserved register and preserves it across context
switches. GCC gets in the way a little bit because it by default assumes
that TLS is accessible from negative %fs offsets (which would
necessitate a kernel-assisted solution). Fortunately, there is a GCC
option to suppress this assumption.

• Introduce the concept of virtual registers, with VREG_TP (thread pointer) being the first of them
• Preserve VREG_TP in context_save/restore()
• Stop using sys_tls_set() in favour of using %fs:0 as the thread pointer
• Make GCC generate code that always goes through %gs:0 to access TLS
• Introduce kseg: a per-CPU area accessible from GS_KERNEL that holds the kernel stack, kernel FS base and a scratch space for syscall and int handlers to use

[1] Drepper, U.: ELF Handling For Thread-Local Storage

File:

• kernel/arch/amd64/src/asm.S (modified) (6 diffs)

kernel/arch/amd64/src/asm.S

@@ -31 +31 @@
 #include <arch/mm/page.h>
 #include <arch/istate_struct.h>
+#include <arch/kseg_struct.h>
+#include <arch/cpu.h>
 
 .text
@@ -178 +180 @@
                 subq $(ISTATE_SOFT_SIZE + 8), %rsp
         .endif
-        
+
         /*
          * Save the general purpose registers.
@@ -199 +201 @@
 
         /*
+         * Is this trap from the kernel?
+         */
+        cmpq $(GDT_SELECTOR(KTEXT_DES)), ISTATE_OFFSET_CS(%rsp)
+        jz 0f
+
+        /*
+         * Switch to kernel FS base.
+         */
+        swapgs
+        movl $AMD_MSR_FS, %ecx
+        movl %gs:KSEG_OFFSET_FSBASE, %eax
+        movl %gs:KSEG_OFFSET_FSBASE+4, %edx
+        wrmsr
+        swapgs
+
+        /*
          * Imitate a regular stack frame linkage.
          * Stop stack traces here if we came from userspace.
          */
-        xorl %edx, %edx
-        cmpq $(GDT_SELECTOR(KTEXT_DES)), ISTATE_OFFSET_CS(%rsp)
+0:      movl $0x0, %edx
         cmovnzq %rdx, %rbp
 
@@ -272 +289 @@
         swapgs
         
-        /*
-         * %gs:0 Scratch space for this thread's user RSP
-         * %gs:8 Address to be used as this thread's kernel RSP
-         */
-        
-        movq %rsp, %gs:0  /* save this thread's user RSP */
-        movq %gs:8, %rsp  /* set this thread's kernel RSP */
-        
+        movq %rsp, %gs:KSEG_OFFSET_USTACK_RSP  /* save this thread's user RSP */
+        movq %gs:KSEG_OFFSET_KSTACK_RSP, %rsp  /* set this thread's kernel RSP */
+
         /*
          * Note that the space needed for the imitated istate structure has been
@@ -308 +320 @@
 
         /*
+         * Switch to kernel FS base.
+         */
+        movl $AMD_MSR_FS, %ecx
+        movl %gs:KSEG_OFFSET_FSBASE, %eax
+        movl %gs:KSEG_OFFSET_FSBASE+4, %edx
+        wrmsr
+        movq ISTATE_OFFSET_RDX(%rsp), %rdx      /* restore 3rd argument */
+
+        /*
          * Save the return address and the userspace stack on locations that
          * would normally be taken by them.
          */
-        movq %gs:0, %rax
+        movq %gs:KSEG_OFFSET_USTACK_RSP, %rax
         movq %rax, ISTATE_OFFSET_RSP(%rsp)
         movq %rcx, ISTATE_OFFSET_RIP(%rsp)
@@ -325 +346 @@
         swapgs
         sti
-        
+
         /* Copy the 4th argument where it is expected  */
         movq %r10, %rcx