Changeset 1df224c in mainline for uspace/drv/nic/e1k/e1k.h


Ignore:
Timestamp:
2011-12-13T16:31:20Z (12 years ago)
Author:
Martin Decky <martin@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
b402dadd
Parents:
63bcbbc
Message:

e1k: initial code revision

File:
1 edited

Legend:

Unmodified
Added
Removed

  • uspace/drv/nic/e1k/e1k.h

    r63bcbbc r1df224c  
    2727 */
    2828
    29 /** @file e1000_defs.h
    30  *
    31  *  Registers, bit positions and masks definition of the E1000 network family
    32  *  cards
     29/** @file e1k.h
     30 *
     31 * Registers, bit positions and masks definition of the E1000 network family
     32 * cards
     33 *
    3334 */
    3435
    35 #ifndef E1000_DEFS_H_INCLUDED_
    36 #define E1000_DEFS_H_INCLUDED_
     36#ifndef E1K_H_
     37#define E1K_H_
    3738
    3839/** Ethernet CRC size after packet received in rx_descriptor */
    39 #define E1000_CRC_SIZE 4
     40#define E1000_CRC_SIZE  4
     41
     42#define VET_VALUE  0x8100
     43
     44#define E1000_RAL_ARRAY(n)   (E1000_RAL + ((n) * 8))
     45#define E1000_RAH_ARRAY(n)   (E1000_RAH + ((n) * 8))
     46#define E1000_VFTA_ARRAY(n)  (E1000_VFTA + (0x04 * (n)))
    4047
    4148/** Receive descriptior */
    … …  
    7582/** VLAN tag bits */
    7683enum e1000_vlantag {
    77         VLANTAG_CFI = (1 << 12), /**< Canonical Form Indicator */
    78 };
    79 
    80 /** transmit descriptor COMMAND field bits */
     84        VLANTAG_CFI = (1 << 12),  /**< Canonical Form Indicator */
     85};
     86
     87/** Transmit descriptor COMMAND field bits */
    8188enum e1000_txdescriptor_command {
    82         TXDESCRIPTOR_COMMAND_VLE = (1 << 6), /**< VLAN Packet Enable */
    83         TXDESCRIPTOR_COMMAND_RS = (1 << 3), /**< Report Status */
    84         TXDESCRIPTOR_COMMAND_IFCS = (1 << 1), /**< Insert FCS */
    85         TXDESCRIPTOR_COMMAND_EOP = (1 << 0) /**< End Of Packet */
    86 };
    87 
    88 /** transmit descriptor STATUS field bits */
     89        TXDESCRIPTOR_COMMAND_VLE = (1 << 6),   /**< VLAN Packet Enable */
     90        TXDESCRIPTOR_COMMAND_RS = (1 << 3),    /**< Report Status */
     91        TXDESCRIPTOR_COMMAND_IFCS = (1 << 1),  /**< Insert FCS */
     92        TXDESCRIPTOR_COMMAND_EOP = (1 << 0)    /**< End Of Packet */
     93};
     94
     95/** Transmit descriptor STATUS field bits */
    8996enum e1000_txdescriptor_status {
    90         TXDESCRIPTOR_STATUS_DD = (1 << 0) /**< Descriptor Done */
    91 };
    92 
    93 #define VET_VALUE 0x8100
    94 
    95 /** e1000 Registers */
     97        TXDESCRIPTOR_STATUS_DD = (1 << 0)  /**< Descriptor Done */
     98};
     99
     100/** E1000 Registers */
    96101enum e1000_registers {
    97         E1000_CTRL = 0x0, /**< Device Control Register */
    98         E1000_STATUS = 0x8, /**< Device Status Register */
    99         E1000_EERD = 0x14, /**< EEPROM Read Register */
    100         E1000_TCTL = 0x400, /**< Transmit Control Register */
    101         E1000_TIPG = 0x410, /**< Transmit IPG Register */
    102         E1000_TDBAL = 0x3800, /**< Transmit Descriptor Base Address Low */
    103         E1000_TDBAH = 0x3804, /**< Transmit Descriptor Base Address High */
    104         E1000_TDLEN = 0x3808, /**< Transmit Descriptor Length */
    105         E1000_TDH = 0x3810, /**< Transmit Descriptor Head */
    106         E1000_TDT = 0x3818, /**< Transmit Descriptor Tail */
    107         E1000_RCTL = 0x100, /**< Receive Control Register */
    108         E1000_RDBAL = 0x2800, /**< Receive Descriptor Base Address Low */
    109         E1000_RDBAH = 0x2804, /**< Receive Descriptor Base Address High */
    110         E1000_RDLEN = 0x2808, /**< Receive Descriptor Length */
    111         E1000_RDH = 0x2810, /**< Receive Descriptor Head */
    112         E1000_RDT = 0x2818, /**< Receive Descriptor Tail */
    113         E1000_RAL = 0x5400, /**< Receive Address Low */
    114         E1000_RAH = 0x5404, /**< Receive Address High */
    115         E1000_VFTA = 0x5600, /**< VLAN Filter Table Array */
    116         E1000_VET = 0x38, /**< VLAN Ether Type */
    117         E1000_FCAL = 0x28, /**< Flow Control Address Low */
    118         E1000_FCAH = 0x2C, /**< Flow Control Address High */
    119         E1000_FCTTV = 0x170, /**< Flow Control Transmit Timer Value */
    120         E1000_FCT = 0x30, /**< Flow Control Type */
    121         E1000_ICR = 0xC0, /**< Interrupt Cause Read Register */
    122         E1000_ITR = 0xC4, /**< Interrupt Throttling Register */
    123         E1000_IMS = 0xD0, /**< Interrupt Mask Set/Read Register */
    124         E1000_IMC = 0xD8 /**< Interrupt Mask Clear Register */
    125 }; 
    126 #define E1000_RAL_ARRAY(n)  (E1000_RAL + ((n) * 8))
    127 #define E1000_RAH_ARRAY(n)  (E1000_RAH + ((n) * 8))
    128 #define E1000_VFTA_ARRAY(n)  (E1000_VFTA + (0x4 * (n)))
     102        E1000_CTRL = 0x0,      /**< Device Control Register */
     103        E1000_STATUS = 0x8,    /**< Device Status Register */
     104        E1000_EERD = 0x14,     /**< EEPROM Read Register */
     105        E1000_TCTL = 0x400,    /**< Transmit Control Register */
     106        E1000_TIPG = 0x410,    /**< Transmit IPG Register */
     107        E1000_TDBAL = 0x3800,  /**< Transmit Descriptor Base Address Low */
     108        E1000_TDBAH = 0x3804,  /**< Transmit Descriptor Base Address High */
     109        E1000_TDLEN = 0x3808,  /**< Transmit Descriptor Length */
     110        E1000_TDH = 0x3810,    /**< Transmit Descriptor Head */
     111        E1000_TDT = 0x3818,    /**< Transmit Descriptor Tail */
     112        E1000_RCTL = 0x100,    /**< Receive Control Register */
     113        E1000_RDBAL = 0x2800,  /**< Receive Descriptor Base Address Low */
     114        E1000_RDBAH = 0x2804,  /**< Receive Descriptor Base Address High */
     115        E1000_RDLEN = 0x2808,  /**< Receive Descriptor Length */
     116        E1000_RDH = 0x2810,    /**< Receive Descriptor Head */
     117        E1000_RDT = 0x2818,    /**< Receive Descriptor Tail */
     118        E1000_RAL = 0x5400,    /**< Receive Address Low */
     119        E1000_RAH = 0x5404,    /**< Receive Address High */
     120        E1000_VFTA = 0x5600,   /**< VLAN Filter Table Array */
     121        E1000_VET = 0x38,      /**< VLAN Ether Type */
     122        E1000_FCAL = 0x28,     /**< Flow Control Address Low */
     123        E1000_FCAH = 0x2C,     /**< Flow Control Address High */
     124        E1000_FCTTV = 0x170,   /**< Flow Control Transmit Timer Value */
     125        E1000_FCT = 0x30,      /**< Flow Control Type */
     126        E1000_ICR = 0xC0,      /**< Interrupt Cause Read Register */
     127        E1000_ITR = 0xC4,      /**< Interrupt Throttling Register */
     128        E1000_IMS = 0xD0,      /**< Interrupt Mask Set/Read Register */
     129        E1000_IMC = 0xD8       /**< Interrupt Mask Clear Register */
     130};
    129131
    130132/** EEPROM Read Register fields */
    131133enum e1000_eerd {
    132         EERD_START = (1 << 0), /**< Start Read */
    133         EERD_DONE = (1 << 4), /**< Read Done */
    134         EERD_DONE_82541XX_82547GI_EI = (1 << 1), /**<   Read Done for
    135                                                                                           *             82541xx and 82547GI/EI
    136                                                                                           */
    137         EERD_ADDRESS_OFFSET = 8, /**< Read Address offset */
    138         EERD_ADDRESS_OFFSET_82541XX_82547GI_EI = 2, /**<        Read Address offset
    139                                                                                                  *              82541xx and 82547GI/EI
    140                                                                                                  */
    141         EERD_DATA_OFFSET = 16 /**< Read Data */
     134        /** Start Read */
     135        EERD_START = (1 << 0),
     136        /** Read Done */
     137        EERD_DONE = (1 << 4),
     138        /** Read Done for 82541xx and 82547GI/EI */
     139        EERD_DONE_82541XX_82547GI_EI = (1 << 1),
     140        /** Read Address offset */
     141        EERD_ADDRESS_OFFSET = 8,
     142        /** Read Address offset for 82541xx and 82547GI/EI */
     143        EERD_ADDRESS_OFFSET_82541XX_82547GI_EI = 2,
     144        /** Read Data */
     145        EERD_DATA_OFFSET = 16
    142146};
    143147
    144148/** Device Control Register fields */
    145149enum e1000_ctrl {
    146         CTRL_FD = (1 << 0), /**< Full-Duplex */
    147         CTRL_LRST = (1 << 3), /**< Link Reset */
    148         CTRL_ASDE = (1 << 5), /*< Auto-Speed Detection Enable */
    149         CTRL_SLU = (1 << 6), /**< Set Link Up */
    150         CTRL_ILOS = (1 << 7), /**< Invert Loss-of-Signal */
    151 
    152         CTRL_SPEED_SHIFT = 8, /**< Speed selection shift */
    153         CTRL_SPEED_SIZE = 2, /**< Speed selection size */
    154         CTRL_SPEED_ALL = ((1 << CTRL_SPEED_SIZE) - 1), /**< Speed selection all
    155                                                                                                          *      bit set value
    156                                                                                                          */
    157         CTRL_SPEED_MASK = CTRL_SPEED_ALL << CTRL_SPEED_SHIFT, /**< Speed selection
    158                                                                                                                         * shift
    159                                                                                                                         */
    160         CTRL_SPEED_10 = 0, /**< Speed selection 10 Mb/s value */
    161         CTRL_SPEED_100 = 1, /**< Speed selection 10 Mb/s value */
    162         CTRL_SPEED_1000 = 2, /**< Speed selection 10 Mb/s value */
    163 
    164         CTRL_FRCSPD = (1 << 11), /**< Force Speed */
    165         CTRL_FRCDPLX = (1 << 12), /**< Force Duplex */
    166         CTRL_RST = (1 << 26), /**< Device Reset */
    167         CTRL_VME = (1 << 30), /**< VLAN Mode Enable */
    168         CTRL_PHY_RST = (1 << 31) /**< PHY Reset */
     150        CTRL_FD = (1 << 0),    /**< Full-Duplex */
     151        CTRL_LRST = (1 << 3),  /**< Link Reset */
     152        CTRL_ASDE = (1 << 5),  /**< Auto-Speed Detection Enable */
     153        CTRL_SLU = (1 << 6),   /**< Set Link Up */
     154        CTRL_ILOS = (1 << 7),  /**< Invert Loss-of-Signal */
     155       
     156        /** Speed selection shift */
     157        CTRL_SPEED_SHIFT = 8,
     158        /** Speed selection size */
     159        CTRL_SPEED_SIZE = 2,
     160        /** Speed selection all bit set value */
     161        CTRL_SPEED_ALL = ((1 << CTRL_SPEED_SIZE) - 1),
     162        /** Speed selection shift */
     163        CTRL_SPEED_MASK = CTRL_SPEED_ALL << CTRL_SPEED_SHIFT,
     164        /** Speed selection 10 Mb/s value */
     165        CTRL_SPEED_10 = 0,
     166        /** Speed selection 10 Mb/s value */
     167        CTRL_SPEED_100 = 1,
     168        /** Speed selection 10 Mb/s value */
     169        CTRL_SPEED_1000 = 2,
     170       
     171        CTRL_FRCSPD = (1 << 11),   /**< Force Speed */
     172        CTRL_FRCDPLX = (1 << 12),  /**< Force Duplex */
     173        CTRL_RST = (1 << 26),      /**< Device Reset */
     174        CTRL_VME = (1 << 30),      /**< VLAN Mode Enable */
     175        CTRL_PHY_RST = (1 << 31)   /**< PHY Reset */
    169176};
    170177
    171178/** Device Status Register fields */
    172179enum e1000_status {
    173         STATUS_FD = (1 << 0), /**< Link Full Duplex configuration Indication */
    174         STATUS_LU = (1 << 1), /**< Link Up Indication */
    175 
    176         STATUS_SPEED_SHIFT = 6, /**< Link speed setting shift */
    177         STATUS_SPEED_SIZE = 2, /**< Link speed setting size */
    178         STATUS_SPEED_ALL = ((1 << STATUS_SPEED_SIZE) - 1), /**< Link speed setting
    179                                                                                                                 *       all bits set
    180                                                                                                                 */
    181         STATUS_SPEED_10 = 0, /**< Link speed setting 10 Mb/s value */
    182         STATUS_SPEED_100 = 1, /**< Link speed setting 100 Mb/s value */
    183         STATUS_SPEED_1000A = 2, /**< Link speed setting 1000 Mb/s value variant A */
    184         STATUS_SPEED_1000B = 3, /**< Link speed setting 1000 Mb/s value variant B */
    185 };
    186 
    187 /** Transmit IPG Register fields
     180        STATUS_FD = (1 << 0),  /**< Link Full Duplex configuration Indication */
     181        STATUS_LU = (1 << 1),  /**< Link Up Indication */
     182       
     183        /** Link speed setting shift */
     184        STATUS_SPEED_SHIFT = 6,
     185        /** Link speed setting size */
     186        STATUS_SPEED_SIZE = 2,
     187        /** Link speed setting all bits set */
     188        STATUS_SPEED_ALL = ((1 << STATUS_SPEED_SIZE) - 1),
     189        /** Link speed setting 10 Mb/s value */
     190        STATUS_SPEED_10 = 0,
     191        /** Link speed setting 100 Mb/s value */
     192        STATUS_SPEED_100 = 1,
     193        /** Link speed setting 1000 Mb/s value variant A */
     194        STATUS_SPEED_1000A = 2,
     195        /** Link speed setting 1000 Mb/s value variant B */
     196        STATUS_SPEED_1000B = 3,
     197};
     198
     199/** Transmit IPG Register fields
     200 *
    188201 * IPG = Inter Packet Gap
     202 *
    189203 */
    190204enum e1000_tipg {
    191         TIPG_IPGT_SHIFT = 0, /**< IPG Transmit Time shift */
    192         TIPG_IPGR1_SHIFT = 10, /**< IPG Receive Time 1 */
    193         TIPG_IPGR2_SHIFT = 20 /**< IPG Receive Time 2 */
     205        TIPG_IPGT_SHIFT = 0,    /**< IPG Transmit Time shift */
     206        TIPG_IPGR1_SHIFT = 10,  /**< IPG Receive Time 1 */
     207        TIPG_IPGR2_SHIFT = 20   /**< IPG Receive Time 2 */
    194208};
    195209
    196210/** Transmit Control Register fields */
    197211enum e1000_tctl {
    198         TCTL_EN = (1 << 1), /**< Transmit Enable */
    199         TCTL_PSP =  (1 << 3), /**< Pad Short Packets */
    200         TCTL_CT_SHIFT = 4, /**< Collision Threshold shift */
    201         TCTL_COLD_SHIFT = 12 /**< Collision Distance shift */
     212        TCTL_EN = (1 << 1),    /**< Transmit Enable */
     213        TCTL_PSP =  (1 << 3),  /**< Pad Short Packets */
     214        TCTL_CT_SHIFT = 4,     /**< Collision Threshold shift */
     215        TCTL_COLD_SHIFT = 12   /**< Collision Distance shift */
    202216};
    203217
    204218/** ICR register fields */
    205219enum e1000_icr {
    206         ICR_TXDW = (1 << 0), /**< Transmit Descriptor Written Back */
    207         ICR_RXT0 = (1 << 7) /**< Receiver Timer Interrupt */
     220        ICR_TXDW = (1 << 0),  /**< Transmit Descriptor Written Back */
     221        ICR_RXT0 = (1 << 7)   /**< Receiver Timer Interrupt */
    208222};
    209223
    210224/** RAH register fields */
    211225enum e1000_rah {
    212         RAH_AV = (1 << 31) /**< Address Valid */
     226        RAH_AV = (1 << 31)   /**< Address Valid */
    213227};
    214228
    215229/** RCTL register fields */
    216230enum e1000_rctl {
    217         RCTL_EN = (1 << 1), /**< Receiver Enable */
    218         RCTL_SBP = (1 << 2), /**< Store Bad Packets */
    219         RCTL_UPE = (1 << 3), /**< Unicast Promiscuous Enabled */
    220         RCTL_MPE = (1 << 4), /**< Multicast Promiscuous Enabled */
    221         RCTL_BAM = (1 << 15), /**< Broadcast Accept Mode */
    222         RCTL_VFE = (1 << 18) /**< VLAN Filter Enable */
     231        RCTL_EN = (1 << 1),    /**< Receiver Enable */
     232        RCTL_SBP = (1 << 2),   /**< Store Bad Packets */
     233        RCTL_UPE = (1 << 3),   /**< Unicast Promiscuous Enabled */
     234        RCTL_MPE = (1 << 4),   /**< Multicast Promiscuous Enabled */
     235        RCTL_BAM = (1 << 15),  /**< Broadcast Accept Mode */
     236        RCTL_VFE = (1 << 18)   /**< VLAN Filter Enable */
    223237};
    224238
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