Ignore:
Timestamp:
2018-03-26T12:35:30Z (6 years ago)
Author:
Jiri Svoboda <jiri@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
48974d6
Parents:
064e0fd
git-author:
Jiri Svoboda <jiri@…> (2018-03-25 18:34:49)
git-committer:
Jiri Svoboda <jiri@…> (2018-03-26 12:35:30)
Message:

Move assembler code out of .h files.

File:
1 edited

Legend:

Unmodified
Added
Removed

  • kernel/arch/sparc64/include/arch/trap/sun4u/mmu.h

    r064e0fd r5a01f7d  
    5656
    5757#ifdef __ASSEMBLER__
    58 
    59 .macro FAST_INSTRUCTION_ACCESS_MMU_MISS_HANDLER
    60         /*
    61          * First, try to refill TLB from TSB.
    62          */
    63 #ifdef CONFIG_TSB
    64         ldxa [%g0] ASI_IMMU, %g1                        ! read TSB Tag Target Register
    65         ldxa [%g0] ASI_IMMU_TSB_8KB_PTR_REG, %g2        ! read TSB 8K Pointer
    66         ldda [%g2] ASI_NUCLEUS_QUAD_LDD, %g4            ! 16-byte atomic load into %g4 and %g5
    67         cmp %g1, %g4                                    ! is this the entry we are looking for?
    68         bne,pn %xcc, 0f
    69         nop
    70         stxa %g5, [%g0] ASI_ITLB_DATA_IN_REG            ! copy mapping from ITSB to ITLB
    71         retry
    72 #endif
    73 
    74 0:
    75         wrpr %g0, PSTATE_PRIV_BIT | PSTATE_AG_BIT, %pstate
    76         mov TT_FAST_INSTRUCTION_ACCESS_MMU_MISS, %g2
    77         mov VA_IMMU_TAG_ACCESS, %g5
    78         ldxa [%g5] ASI_IMMU, %g5                        ! read the faulting Context and VPN
    79         PREEMPTIBLE_HANDLER exc_dispatch
    80 .endm
    81 
    82 .macro FAST_DATA_ACCESS_MMU_MISS_HANDLER tl
    83         /*
    84          * First, try to refill TLB from TSB.
    85          */
    86 
    87 #ifdef CONFIG_TSB
    88         ldxa [%g0] ASI_DMMU, %g1                        ! read TSB Tag Target Register
    89         srlx %g1, TSB_TAG_TARGET_CONTEXT_SHIFT, %g2     ! is this a kernel miss?
    90         brz,pn %g2, 0f
    91         ldxa [%g0] ASI_DMMU_TSB_8KB_PTR_REG, %g3        ! read TSB 8K Pointer
    92         ldda [%g3] ASI_NUCLEUS_QUAD_LDD, %g4            ! 16-byte atomic load into %g4 and %g5
    93         cmp %g1, %g4                                    ! is this the entry we are looking for?
    94         bne,pn %xcc, 0f
    95         nop
    96         stxa %g5, [%g0] ASI_DTLB_DATA_IN_REG            ! copy mapping from DTSB to DTLB
    97         retry
    98 #endif
    99 
    100         /*
    101          * Second, test if it is the portion of the kernel address space
    102          * which is faulting. If that is the case, immediately create
    103          * identity mapping for that page in DTLB. VPN 0 is excluded from
    104          * this treatment.
    105          *
    106          * Note that branch-delay slots are used in order to save space.
    107          */
    108 0:
    109         sethi %hi(fast_data_access_mmu_miss_data_hi), %g7
    110         wr %g0, ASI_DMMU, %asi
    111         ldxa [VA_DMMU_TAG_ACCESS] %asi, %g1             ! read the faulting Context and VPN
    112         ldx [%g7 + %lo(tlb_tag_access_context_mask)], %g2
    113         andcc %g1, %g2, %g3                             ! get Context
    114         bnz %xcc, 0f                                    ! Context is non-zero
    115         andncc %g1, %g2, %g3                            ! get page address into %g3
    116         bz  %xcc, 0f                                    ! page address is zero
    117         ldx [%g7 + %lo(end_of_identity)], %g4
    118         cmp %g3, %g4
    119         bgeu %xcc, 0f
    120 
    121         ldx [%g7 + %lo(kernel_8k_tlb_data_template)], %g2
    122         add %g3, %g2, %g2
    123         stxa %g2, [%g0] ASI_DTLB_DATA_IN_REG            ! identity map the kernel page
    124         retry
    125 
    126         /*
    127          * Third, catch and handle special cases when the trap is caused by
    128          * the userspace register window spill or fill handler. In case
    129          * one of these two traps caused this trap, we just lower the trap
    130          * level and service the DTLB miss. In the end, we restart
    131          * the offending SAVE or RESTORE.
    132          */
    133 0:
    134 .if (\tl > 0)
    135         wrpr %g0, 1, %tl
    136 .endif
    137 
    138         /*
    139          * Switch from the MM globals.
    140          */
    141         wrpr %g0, PSTATE_PRIV_BIT | PSTATE_AG_BIT, %pstate
    142 
    143         mov TT_FAST_DATA_ACCESS_MMU_MISS, %g2
    144         ldxa [VA_DMMU_TAG_ACCESS] %asi, %g5             ! read the faulting Context and VPN
    145         PREEMPTIBLE_HANDLER exc_dispatch
    146 .endm
    147 
    148 .macro FAST_DATA_ACCESS_PROTECTION_HANDLER tl
    149         /*
    150          * The same special case as in FAST_DATA_ACCESS_MMU_MISS_HANDLER.
    151          */
    152 
    153 .if (\tl > 0)
    154         wrpr %g0, 1, %tl
    155 .endif
    156 
    157         /*
    158          * Switch from the MM globals.
    159          */
    160         wrpr %g0, PSTATE_PRIV_BIT | PSTATE_AG_BIT, %pstate
    161 
    162         mov TT_FAST_DATA_ACCESS_PROTECTION, %g2
    163         mov VA_DMMU_TAG_ACCESS, %g5
    164         ldxa [%g5] ASI_DMMU, %g5                        ! read the faulting Context and VPN
    165         PREEMPTIBLE_HANDLER exc_dispatch
    166 .endm
    167 
     58#include <arch/trap/sun4u/mmu.S>
    16859#endif /* __ASSEMBLER__ */
    16960
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