Changeset b26396e in mainline for kernel/arch/amd64/src/fpu_context.c


Ignore:
Timestamp:
2012-12-29T22:16:16Z (11 years ago)
Author:
Jan Vesely <jano.vesely@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
26e550c2
Parents:
ce60be1 (diff), b55877d (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.
Message:

Mainline changes

File:
1 edited

Legend:

Unmodified
Added
Removed

  • kernel/arch/amd64/src/fpu_context.c

    rce60be1 rb26396e  
    5757{
    5858        /* TODO: Zero all SSE, MMX etc. registers */
     59        /* Default value of SCR register is 0x1f80,
     60         * it masks all FPU exceptions*/
    5961        asm volatile (
    6062                "fninit\n"
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